Realized objectives of the visit

1. Electrical characterization of the PureB and PureGaB layers and devices. During the visit to Host organization, research on electrical characterization of PureB/PureGaB layers continued by studying MBE deposited PureB layers on Si test structures and PureGaB Ge-on-Si devices. Analysing MBE deposited PureB layers and devices it was observed that there is a clear difference in surface textures which can be explained by a reduction in mobility of the B atoms along the surface as the substrate temperature decreases. Little more than 1.5-nm-thick PureB layers deposited by MBE at Si substrate temperatures from 400 °C down to 50 °C were shown to form p+n-like diodes due to an effective suppression of electron injection from the n-substrate. The efficiency decreases with substrate temperature, and for 50 °C it is about a factor of 50 lower than for Tsub = 400 °C and the RSH increased by decades. This was shown to be correlated to a less compact nature of the deposited PureB material, which was observed as an increase in roughness compared to CVD depositions, a higher etch rate of the layer in Al-etchant, and degradation of the masking of Si etching in TMAH. At Tsub = 400 °C the MBE-deposited PureB diodes display the same low Ie and RSH as CVD-deposited PureB diodes, which suggests that the reaction at the Si surface responsible for the attractive electrical behavior is predominantly determined by the activation energy supplied by the surface temperature. Electrical characterization of PureGaB Ge-on-Si devices displayed high performance of the devices in terms of low leakage currents and broadband detection owed to the shallow PureGaB layer at the surface. Electrical characterization at low temperatures revealed that the diode current is predominantly determined by pn junction at the PureGaB/Ge interface. However, Ge/Si heterostructure had detrimental effect on responsivity in the NIR range which was also confirmed by a simulation study.

2. Modeling of the PureB and PureGaB layer. Experimental knowledge obtained by electrical and material characterization performed at the Host institution was used as an input data for a simulation study which improved original PureB TCAD model. For CVD deposited layers it was found that below 450 ºC the Ie appears to saturate at ~ 45 pA, which corresponds to a saturation current density of 9.6×10‑20 A/µm2. Devices with MBE PureB deposited at Tsub = 300 °C and 400 °C follow the same trend and almost the same suppression of electron injection is achieved. However, decreasing the deposition temperature down to 200 °C and 50 °C increases electron current to 330 pA and 2.45 nA which correspond to saturation current densities of 7×10‑19 A/µm2 and 5.2×10‑18 A/µm2, respectively. The large increase in electron injection at 50 °C suggests that the interface bonding between the B and Si that leads to hole accumulation at the interface is still taking place albeit not very effectively. Comparing experimental results on PureGaB Ge-on-Si devices to simulations, first functional TCAD model of the layer was constructed which was later used for optimization of PureGaB Ge-on-Si devices.

3. New photodiode structures with PureGaB layers. PureGaB model developed in O3 was further used in the simulations to optimize the structure with respect to increasing breakdown voltage and responsivity. Measured breakdown voltage in Ge-on-Si devices is -30 V. From the light emission measurements and simulation, it was observed that the critical part of the design is perimeter of the Ge-on-Si island and Ge/Si heterojunction. New process flow was proposed which would eliminate the impact of Al deposition on degradation of the Ge/Si interface. TCAD simulations of Ge-on-Si APDs show that the breakdown at the perimeter could be optimized by additional guard rings at the island perimeter. Breakdown voltage higher than -30 V could be achieved. A simulation study on MIPQR and SQE shows that PureB layer thicker than 10 nm is capable of quenching the avalanche when integrated in an anode region of a SPAD. PureB layer does not significantly impede the optical generation in Si when used as an entrance window of a SPAD for light detection of wavelengths between 0.4 µm and 1 µm. Reduction of optical generation in Si can be lower than 5 % for 5 nm thick PureB at 0.7 µm. PureB anode-integrated highly transparent quenching resistor is an easy solution which could improve the overall responsivity compared to thin film resistor solutions or increase the fill factor of diodes when employed in SPAD arrays.